LDO (Low Drop-Out) regulators are very commonly used and may have different structures. The present invention is directed to improving LDO regulators which have structures in accordance with FIG. 1. Such LDO regulator comprises a differential amplifier 10, a gain stage 20 and an output stage 30.
The differential amplifier 10 has a reference input terminal 1, a feedback input terminal 2 and an output terminal 3.
The gain stage 20 comprises a bias resistor 21 and a MOS transistor 22. This MOS transistor 22 has a first main terminal which is connected to a first terminal 100 of a power supply unit of the LDO regulator. A second main terminal of the MOS transistor 22 is connected to a second terminal 101 of the power supply unit through the bias resistor 21, and a gate terminal of the MOS transistor 22 is connected to the output terminal 3 of the differential amplifier 10.
The output stage 30 comprises a switch, here in the form a transistor 31, in the following referred to as “the powerMOS transistor 31”, and a pull-down path 32. The powerMOS transistor 31 has a first main terminal which is connected to the terminal 100 of the power supply unit through the pull-down path 32, a second main terminal which is connected to the terminal 101 of the power supply unit, and a gate terminal which is connected to a node of the gain stage 20 between the bias resistor 21 and the MOS transistor 22. The output stage 30 further comprises a node between the powerMOS transistor 31 and the pull-down path 32 which forms an output terminal 33 of the LDO regulator. The pull-down path 32 comprises itself a feedback output terminal 34 which is designed for supplying a feedback voltage representative for an LDO output voltage VOUT existing at the output terminal 33 of the LDO regulator. This feedback output terminal 34 is connected to the feedback input terminal 2 of the differential amplifier 10.
The powerMOS transistor 31 and the MOS transistor 22 of the gain stage 20 are of opposite transistor types. For illustration purpose, the voltage of the second terminal 101 of the power supply unit (not represented) is higher than that of the first terminal 100, this latter being represented as a grounded terminal. Then, the powerMOS transistor 31 is of p-type, and the MOS transistor 22 is of n-type. The types of all transistors considered in the present specification are to be exchanged if the polarity of the power supply unit is swapped between the terminals 100 and 101.
Reference 1000 denotes generally such LDO regulator as a whole. A load resistance Rload is connected between the output terminal 33 of the LDO regulator 1000 and the terminal 100 of the power supply unit. Cload denotes a decoupling capacitor used commonly but optionally in a known manner at the output terminal 33 of the LDO regulator 1000.
Also in a known manner, resistor R and capacitor C are arranged for ensuring stability of the LDO regulator 1000. They are optional and not related to the present invention. Other arrangements are also known for compensating frequency effect.
The following voltages are also indicated in FIG. 1:                VREF: voltage applied on the reference input terminal 1,        VBAT: output voltage of the power supply unit,        VB1: bias-voltage applied to the differential amplifier 10,        VO1: output voltage supplied by the differential amplifier 10 to the gate terminal of the MOS transistor 22,        VGATE voltage supplied by the gain stage 20 to the gate electrode of the powerMOS transistor 31,        VOUT: voltage existing at the output terminal 33 of the LDO regulator 1000, and        VFB: feedback voltage supplied by the pull-down path 32 and transmitted to the feedback input terminal 2 of the differential amplifier 10.        
For example purpose, the pull-down path 32 comprises two series-connected resistors RFB1 and RFB2, with a node intermediate to these latter resistors which forms the feedback output terminal 34. FIGS. 2a to 2c show other possible structures for the output stage 30. These structures implement different designs for the pull-down path 32, but they are all well-known to the Man skilled in electronics, so that it is useless describing them here. However, the invention disclosed hereunder in the present application may be implemented with any design of the pull-down path 32.
Such LDO regulator in use conducts a current between the terminals 100 and 101 of the power supply unit, in addition to the current fed into the load resistor Rload. This current internal to the LDO regulator 1000 is called consumed current and constitutes energy loss.
When the load resistor Rload is disconnected from the output terminal 33, there still flows a quiescent current through the LDO regulator 1000. A major part of this quiescent current is produced at the interface between the gain stage 20 and the output stage 30, because the output impedance of the gain stage 20 is low for ensuring good dynamic performances. Another part of the quiescent current flows through the powerMOS transistor 31 and the pull-down path 32. For pull-down efficiency, the total resistance of the pull-down path 32 cannot be too high and, even when the powerMOS transistor 31 is in off-state, a leakage current of this powerMOS transistor 31 still flows from the terminal 101 to the terminal 100 through the pull-down path 32. Then, this leakage current participates to the current consumed by the LDO regulator 1000.
The quiescent current is significant when the load resistor Rload is important, i.e. when the output current supplied by the LDO regulator 1000, from the output terminal 33 into the load resistor Rload, is low. This output current is denoted Iload in FIG. 1.
Several circuitry modifications have already been proposed for reducing the consumed current of an LDO regulator, including for small output current values. In particular, document US 2010/0148735 discloses modifying the bias of the differential amplifier and the structure of the gain stage, for obtaining a consumed current which is proportional to the output current of the LDO regulator. This is beneficial for low values of the output current, but detrimental for higher values of the output current. In addition, the structure modifications proposed in US 2010/0148735 require to re-design the LDO regulator topology, and alter the dynamic performances of the LDO regulator over the whole output current range.
Document US 2002/0125866 discloses adding a second output stage specifically adapted for small output current values, in parallel to the output stage commonly used. Then both output stages are operating together when the output current is not limited to small values, and stability issues arise which must be solved separately.
Finally, document JP 10-301642 discloses using a passive leakage consuming circuit which corresponds to the structure shown in FIG. 2c. The circuit of FIG. 3 of this document creates an unregulated pull-down current even if the leakage current can be consumed by the external load. Then, the leakage current is flown uselessly internally to the leakage consuming circuit. For avoiding such situation, the circuit is completed as shown in FIG. 4 of this document so as to switch off the leakage consuming circuit when the external load current exceeds a maximum value. In addition, for both circuits of FIGS. 3 and 4, the leakage current which is conducted through the pull-down path is unregulated.